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    2,993 opencl fpga jobs found, pricing in USD

    To build and test, using Modelsim/ISE Simulator (ISim), a VHDL model of a Direct Digital Synthesiser (DDS) circuit which can them be implement on an FPGA board by using the Xilinx ISE 14.7 software tools to map the design onto the Xilinx Spartan-6 NEXYS-3 development board.

    $196 (Avg Bid)
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    5 bids
    Fpga VHDL help 6 days left

    I need a help with VHDL subject. anyone interested let me know thank you.

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    Hi, I have a board very similar to Ultra96v2. I have a very simple project (with a bare metal application) which works well in Ultra96v2 but it fails in my board. This project just show a color pattern (VTPG) through the DisplayPort. I suspect the failing reason may be related with the to DPPSU driver. I would like to run this sample project on my board and I need some help to debug and fix th...

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    Job Description :- Automate some Perl to System Verilog Files of a switch testbench. Automate for multiple configurations provided in Perl file. For one of the configurations, a reference testbench is provided. Write scripts to automate TB files such that it matches refernce config and generate for all other config. Make sure simvs are getting built and tests are run. Detailed Requirement :- ...

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    Job Description :- Develop Verification Component of PCIE and other protocol devices including Generators, Transactors, Drivers, Transmiter, Receiver and Transmit and Receive Packet Classes. Build Simvs, and develop and Run test-cases using these components. Detailed Requirement :- 1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experien...

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    Embedded software Development 3 days left
    VERIFIED

    We are embarking on embedded software development using Vivado and Vitis Development tool for Xilinx evaluation board. The resource should be experienced with embedded software development Familiar with Armv7 / Armv8 architecture Familiar with Xilinx development tools like Vivado (IDE), Vitis unified software platform, compilers, debuggers and operating system The project is for establis...

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    Hi Pradeep Y., I noticed your profile and would like to offer you my project. We can discuss any details over chat. please discuss first about the work, then accept the proposal. have you done any work on qam / ofdm / ofdm-im implemenation on fpga.

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    I have a short project. I was able to create a working accelerator, but it was not fast enough. I don't have much experience with FPGA. You will need to have experience and be able to answer some questions on the spot to get the job. I am not paying money to have someone try to learn how to do it. Let me know and I will get you the source files of the software I need to be accelerated. The pr...

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    Good afternoon, I am doing a project where I have to implement the FFT RADIX 4 code in an FPGA, in addition to implementing a FFT Logicore Radix4 in the same FPGA. I am looking for someone who can explain how to correctly declare the ports in the FPGA. The codes that I already have it. I need a person that it's expert in FPGA.

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    hi there. i am wondering if you have experience in a subject called Introductory to Digital Systems? i can give you a few topics in subject that you might revogize for example: 1- Combination logic circuits design (binary, decimal numbers) 2- sequential logic circuit design and many topics in the subject as well. if you want me to provide with more topics, i can do that so you can get familiar. al...

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    I need someone who can Implement optimized bitsteam for cvp13. It should be a Bitsteam and miner application. Kawpow algorithm minimum hashrate of 650. From my experience guys are taking a pc miner version that exists for graphic cards modifying it for fpga and building there bitsteam back wards from there. T. rex miner for example is open source and easy to modify

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    I have to perform this on every terminal or reboot. I want it to automatically be done. Please provide the script/instructions to do this. export AWS_FPGA_REPO_DIR=/home/centos/aws-fpga cd $AWS_FPGA_REPO_DIR source [login to view URL] source [login to view URL] // 1 - install compiler and linux kernel toolkit sudo yum groupinstall "Development tools" sudo yum install kernel kernel-d...

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    I am looking for a senior fpga expert who have experience in fpga with verilog language experience

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    Senior FPGA expert required 2 days left
    VERIFIED

    I am looking for a senior fpga expert who have experience in fpga with verilog language experience

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    to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player...

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    Hi Ahmed M., I noticed your project bidding(https://www.freelancer.com/projects/fpga/USB-data-sniffer/details) and would like to offer you my project. We can discuss any details over chat. Thank you.

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    Hello Shweta P., I'm looking for a custom kawpow bitstream and miner for cvp-13 fpga board. Can you do this? If so can you guess an aproximated hashrate? Thank you very much

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    I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

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    I am trying to implement some games in Verilog. I have an Arty S7-50 board and currently I am working on a game like the classic Snake. I am using a PS2 keyboard to control the direction and I am using VGA to display the image. I have some troubles with my code and I need someone to look at it and make it work and add some features. For more details please contact me.

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    Request details FPGA implementation of Neural Network, using Vivado HLS, on the PYNQ board. The python code is available. Need someone know how to write this code in C or C++ and then implement it on FPGA using HLS. The python code and paper are available.

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    FPGA implementation of Neural Network, using Vivado HLS, on the PYNQ board. The python code is available. Need someone know how to write this code in C or C++ and then implement it on FPGA using HLS. The python code and paper are available.

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    Hey, I need help of someone who is specialised in these topics • FPGA – Architecture and CAD • Pico Blaze architecture and coding • UART principles • RT Level Design (Datapath/Controller Design) • Sequential Circuit Design I will let you know the work

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    I need a Yescrypt mining software for FPGA AWS F1 based probably on verilog or vhdl. There is already CPU miner in C for yescrypt/yespower and some verilog for Scrypt algorithm. I need a development of a AFI image to work with Amazon F1 FPGA instances. Let's say an Yescrypt ASIC.

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    - Must have excellent written and verbal communication in English. - Must have at least 1 year of experience in Technical recruiting. - Must have recruited candidates in : * Electronics: ASIC/FPGA/Verilog/Embedded/PCB/CAB * IT: React, Microserverices, Angular, Data Science, Cloud, etc. - Should be available at least 20 hours a week (Monday-Friday), 40 hours is highly preferred. - Good knowledg...

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    Sealed NDA
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    Looking for developing Software and Hardware for Power Electronics Controller using DSP (TMS320xxx), CLPD, FPGA and MCU's Based for power Control through thyristors and IGBT's

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    Xilinx Vivado project Watch HH:MM:SS - Command specification: MODE/SEL, CHG+/UP, CHG-/DN Level 1 implementation - Vivado hierarchical project

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    Hello, I'm looking to build a ETH mining app for Universal Windows Platform (UWP) in C#. This is a proof-of-concept only and so I only need porting of existing open-source miners to UWP and translate code into C#. Existing open-source miners to reference are: ethminer ikminer CUDA support is to be removed, keeping only OpenCL. Are you interested in working together? Peter Deliverables T...

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    Expert on Xilinx Vivado and Zybro Z7 board. Having expertise in VHDL and FPGA. We need to store data that is coming from Zybo Z7 board in text or C file in MircroSD.

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    hello dear, I am looking for someone who is expert in Firmware filed, and know how to work on VHDL,FPGA and can explain it to me very clear way with practical work.

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    Matlab code is written by Xilinx system generator software to realize defocus estimation of single image. The Gaussian function blur in the traditional monocular defocus image restoration process is replaced by Gaussian Cauchy mixture blur. The MATLAB and python codes of traditional defocus estimation methods can be provided for similar papers (the results of vivado HLS). We only need to write a f...

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    I need to get 5 miliseconds data (625000 values of 14 bit each), each time I press a button B1, until DDR3 memory is full. The B1 button must be usable again only after the 5ms of data storing ended. An index counter must be incremented with 625000. If I press a button B2, data must be sent to UART at 115200 baudrate, from memory index 0 to current index (multiples of 625000). The index will NOT...

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    looking fro a fpga Engineer, may you are interested

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    Hi Amir Y., My name is Alon from Israel, I noticed your zen protocol FPGA project, I'm looking to build a more efficient FPGA miner for zen protocol, let's discuss

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    I have multiple tasks related to the following microcontrollers 1) Arduino 2) Raspberry Pi 3) FPGA 4) PIC Microcontroller

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    Hi, I want a simple design with the "Video Pattern Generator + DisplayPort".

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    Need to check my CUDA code and make optimizations

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    I need to help with opencl problem c++

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    Our PowerPC based system is YOCTO Project which is built under Ubuntu 14.04 with Tool Chain GCC Version 4.9.2 over the Kernel 4.1. We use Software Development Kit of the NXP SDK Version "QorIQ Linux SDK v2.0". In our system there are 6 Serial 16550 UART ports configurable to RS232/RS422/RS485. The 6 UARTs are controlled via FPGA. The SoC is connected to the FPGA via IFC bus. Refer to bl...

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    help with qucik opencl project (clGetDeviceInfo)

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    I need you to debug a module in vhdl for me. I would like this to be developed quickly

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    I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.

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    The Project is to develop Verilog code to control DDR4 DRAMs via a Memory Controller and I2C interface using a Xilinx Zync+ UltraScale FPGA.

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    design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

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    design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

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    We're developing a custom HW computer system that will have many video inputs and outputs and will split/resize/distribute the inputed video to the output. It will have an Intel CPU and a custom XiLink FPGA. We're looking for an expert individual that can help us develop the software driver that will manage the FPGA and within a linux environment.

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    ETH: 1 pool is specified Main Ethereum pool is [login to view URL] DCR: 0 pool is specified AMD OpenCL platform not found Be careful with overclocking, use default clocks for first tests Press "s" for current statistics, "0".."9" to turn on/off cards, "r" to reload pools, "e" or "d" to select current pool, "x" to select GPU CUDA...

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