A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .
We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including: 1) FPGA timing closure constraint 2) Place & route issues. 3) Set up clock divider to CL logic. Potentially, we have a lot more work if you
I need a Stepper motor controller code in verilog, the controller should take Frequency, direction and number of steps as an input and generate a S shape signal for Driver IC , based on that signal the driver IC will control the stepper motor .
...Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document...
Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private
I need help completing a Single Cycle RISC-V datapath and control using System Verilog. What I need: - A report including how different instructions have be to implemented. The document contains all the necessary modifications in the datapath to add all the instructions. - Modify the code to implement all the instructions.
need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works
We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers