Despite being away from his family, Vietnam local Van Loi Le continues to support his loved ones back home. How? Through Freelancer!
Synchronous control of 8 stepping motors with calculation of a trajectory of linear motion and circular motion with constant acceleration for CNC machine. SystemVerilog, FPGA Altera (IntelFPGA)
I need someone who is expert in academic writing and EE engineering communication and radar field and also embedded systems FPGA, the page's number will be around 50, and the topic and results and design are ready just need to be written.
We are in need of an experienced developer to help us modify existing drivers based on Java to communicate with a FPGA based Bill validator from a Raspberry pi over USB. We previously modified existing java files to communicate with a bill validator that we later found out was using an old PSD based chip, whereas the new devices are based on FPGA chips. Our old code does not communicate with t...
projekt może być oparty na chipie ADV7181
• Target DDR3 controllers development for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document
Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly cont...
We need to develop a QPSK demodulator FPGA xilinx based.
We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board.
Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details.