Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    163 jobs found, pricing in PHP

    1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic

    ₱1569 / hr (Avg Bid)
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    4 bids

    I would like to implement on error detection amd correction techniques using quartus verilog

    ₱9618 (Avg Bid)
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    16 bids
    Vhdl project 6 days left
    VERIFIED

    Need experts in electrical engineering field especially in FPGA and Embedded systems that are also skilled in vhdl. Please look at the link for more details. Refer to the intro pdf for project requirements and deliverables. Need complete project done even the scripts for presentation and technical report. [url removed, login to view]

    ₱19395 (Avg Bid)
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    12 bids

    I would like to do error detction and correction techniques in verilog and quartus nios ii.

    ₱19540 (Avg Bid)
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    14 bids

    It's a basic home automation project. I am able to control the relay without any problem until i connect it with a ac appliance (bulb).

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    13 bids

    Project for huge experienced engineers. Result: Altium project and firmware. Details of the project in the attachment.

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    1 bids

    The processor I want to design is a 32-bit version of the MIPS processor, however the instruction set only needs to be a small subset of the actual MIPS ISA. It should implement the multicycle datapath version of the processor utilizing the VHDL hardware descriptive language. The processor should support three instruction formats: R-format, I-format, and J-format The memories should be word ad...

    ₱4202 (Avg Bid)
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    I currently have a Xilinx ISE project where I am emulating a 6522 VIA and AY-3-891x Sound Generator for a legacy sound card. See the attached project files (and datasheets if needed). The code is mostly working and well enough to achieve sound, however I believe there could be some issues with the way PWM is implemented as there seems to be distortion in the combined audio output per channel. ...

    ₱21616 (Avg Bid)
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    Hi, I wanted to implement research work on the AES(Advnaced Encryption Standard) algorithm and differential scan attack on the same to retriever secret key. In addition, the prevention mechanism against such attack has to be developed. Coding and simulation in verilog(Xilinix-ISE/Modelsim) will be fine. Also, requires documents for the implementation (step-by-step procedure), block diagram ...

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    I have a dc motor with optical encoder that produces 360 pulse per revolution. I need fuzzy logic control of this motor. Altera de2 does not have an ADC so I have to use external ADC (max1132) to read set value from potentiometer. The set value and current RPM should be displayed on DE2's LCD.

    ₱5568 (Avg Bid)
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    Project for Julius C. 7 days left
    VERIFIED

    Hi can you handle vhdl task ?

    ₱1772 (Avg Bid)
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    2 bids
    VHDL task URGENT 4 days left
    VERIFIED

    Please check the attachment for the details Need to use Quartus ll

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    i want to implement three phase locked loop implemented in simulink

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    Devise a communication protocol/method to communicate to between devices, through RS232. There is one ‘master’ and up to two slaves, which communicate two ways. Slaves will have unique addresses. Code needs to be compatible with ATMEL microcontrollers as this is what will be used. Communication is simple and will take the following form; • Master to slave o Turn output 1 to 8...

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    I need assembly MIPS... thanks

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    Embedded systems -- 2 2 days left
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    Regarding verilog code

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    System Verilog Project 1 day left
    VERIFIED

    It is a System Verilog Project. I will give the details later.

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    I need a tutor for fpga programming in vhdl. I have made some projects but they need to be corrected. I'm working on Xilinx Spartan-6.

    ₱354 / hr (Avg Bid)
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    13 bids

    -Computer System Architecture -Basic Computer Organization and Design -Register Transfer and Microoperations -Digital Components for Integrated Circuits

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    [url removed, login to view] a DE0-Nano FPGA board to a UNO board using two jumper wires for data transfer and one wire to connect their grounds. Write codes that allow the microprocessor to use one wire to send a bit over to the FPGA which inverts the bit and sends it back to the microprocessor using the other wire. The bit value to be sent out from the UNO should be input from the serial mon...

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