Over 2.5 years of experience in Verilog RTL Design, Microcontroller Projects and Algorithm Design in MATLAB in Industry and Academia. My past projects include:
- PHY Layer Design on FPGA for Software Defined Radio PMore
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Some of my projects: [url removed, login to view]
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At hackerrank I have 4707 (Algorithms) and 9000 (Data Structures) ranks.
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