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Altera Quartus Sp13 - Verilog delay/timing project

I have a simple multiplexer circuit that uses off the shelf 74LS logic chips. Years ago this circuit was converted from off the shelf parts to Verilog for a CPLD to save much needed space. The platform selected at the time was Atmel's Chip Designer using the ATF150x CPLD. The Atmel CPLD's are a little large compared to todays offerings. Atmel's software also doesn't run well on any newer PC.

The decision was made to move to a new CPLD platform, that being Altera's Quartus SP13. The CPLD we've selected to use is the 3000A with a pin to pin delay of 10ns.

Due to the new CPLD and new software, our simple multiplexer circuit (written in Verilog) still works but has timing issues. In order to get it to run almost perfect, I have to run the clock input and a control line through a buffer to add some delay. The external 74LS buffer has an average delay of 8ns with a single pass being not enough and 2 passes being too much.

What I require is someone who knows Verilog and Altera's Quartus software very well to take this design and add in the required delays.

Skills: Verilog / VHDL

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About the Employer:
( 0 reviews ) Burilington, Canada

Project ID: #7788352

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ahmedmohamed85

Dear sir I have more than 8 years experience in digital design using verilog and Altera Quartus please check my profile also please message me so that we can discuss waiting your reply best regards

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zarnescugeorge

Hello! I can help you right away! Please look at my profile! I have 10 years experience with altera and verilog! Send me a message! Have a nice day!

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aforencich

This looks like it could be a relatively simple timing constraints issue. Inserting discrete inverters should not be necessary as the toolchain can insert delays, given the correct constraints. I will probably need a More

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cscinstructor

I have read and fully understood your requirements. Please open chat to discuss further….. =================+++++++++++++++++++++++++==================

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