Advanced Verilog FIR Band Pass Filter Implementation

Completed Posted Nov 22, 2014 Paid on delivery
Completed Paid on delivery

I need either a brand new implementation for a BPF FIR filter, or an improvement to the one already uploaded.

For improvements to the uploaded code:

- a handshaking FSM system between the FILTER and the ROM input signal generator

- the filter block should be divided into more modules with better use of multipliers and adders. Also, it's coefficients should not be hardcoded, they should be read from a .COE file

- The Xilinx project should be divided into 3 main parts:

-- Filter part

-- Software Simulation part (with the Input Chirp)

-- Hardware Verification part (Using Chipscope)

- Software to be used: Modelsim 10.1 SE (for an analog view of the signal), and Xilinx ISE Design Suite

Electrical Engineering Electronics Verilog / VHDL

Project ID: #6767767

About the project

5 proposals Remote project Active Nov 27, 2014

Awarded to:

ahmedmohamed85

Hi I am making this bid to know why you need improvements, is it due to poor design or you need extra features, please tell me, waiting your reply best regards

$90 USD in 3 days
(108 Reviews)
6.9

5 freelancers are bidding on average $98 for this job

loi09dt1

A proposal has not yet been provided

$166 USD in 3 days
(13 Reviews)
4.3
jaydeeprangani

My qualification is M.Tech. in VLSI and Embedded System. I have completed my project on FIR filter using verilog in xilinx tool during my curriculum.

$90 USD in 3 days
(1 Review)
0.0
Bordhan

i have good knowledge on DSP and verilog , worked with Modelsim 10.1 SE , and Xilinx ISE Design Suiteand I am capable of doing this.

$72 USD in 3 days
(0 Reviews)
0.0