Dear sir
I have more than 10 years experience in digital design using Verilog please check my profile also please message me so that we can discuss
best regards
Hello,
I am working in the ASIC design flow for 10 years. I have experience in using VCS FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for design multi core chip with 16 core of 16bit MIPS such that I think I can do your task very well. Please see reviews in Verilog project which I complete very well, please ignore a bad review in a website project review. Best Regard.
I did internship for 8 months in vlsi startup and took 6 months course and 2 months internship in my training institution. I'm having good experience in verilog.