We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado.
There are 5 blocks in total with the following functionalities:
1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench.
2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench.
3. Clock-gen: Configure Xilinx PLL to generate the system clock and some divided clocks. Write testbench.
4. Latch block: Write a simple latch logic to control some outputs and testbench.
5. UART: Run verification on our IP with an existing testbench.
More information available for suitable candidates upon request
Dear sir I have more than 10 years experience in digital design using Xilinx FPGA, i can do all the required 5 Tasks perfectly, please message me so that we can discuss Best regards
12 freelancers are bidding on average €444 for this job
Hi! I have successfully finished a lot of FPGA projects, one of them found here, on Freelancer.com, you may find my employer feedback. Please contact me via chat to discuss implementation details of your requirements.
Hello I have over 10 years experience using Xilinx devices and working with Vivado. I would be happy to supply some example code that I have produced if that would be of interest. Thanks Jon
I am experienced fpga ip core developer with a lot of experience on building ip cores. I have experience of working on development of verilog wrappers and testing of uart for virtex7.
I am working on Xilinx FPGAs for 3 yrs from now. Zynq and UltraScale+. Get the smallest block of problem. I will provide the solution. If you liked my way of working. We will go further.