design verification engineer

Closed Posted 1 year ago Paid on delivery
Closed

• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.

• Understanding of verification tools like Simulator, Synthesis etc.

• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL

• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.

• Excellent written and verbal interpersonal skills

• Self-motivated and great teammate

Verilog / VHDL Electronics Microcontroller Electrical Engineering Engineering

Project ID: #34731118

About the project

6 proposals Remote project Active 1 year ago

6 freelancers are bidding on average $52/hour for this job

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an More

$40 USD / hour
(94 Reviews)
6.9
Hbs3401

Hi sir, I am a electronics and communication engineer, I have knowledge of Verilog, System Verilog, UVM. I can write code for this languages more efficiently, If you are interested Please reply me. I am waiting for y More

$60 USD / hour
(2 Reviews)
2.7
convabhi

I am lead verification engineer in nxp india pvt ltd and good knowledge of verilog, system verilog ,uvm and vmm. I have hands on experience on functional coverage and assertions and worked on ahb, axi, apb protocols. H More

$80 USD / hour
(0 Reviews)
0.0
vamsiakula17

working as rtl trainee... hope i would be a great choice for your requirements..i have great amount of knowledge in verilog and good amount of knowledge in sv as well.

$30 USD / hour
(0 Reviews)
0.0