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$5 USD / hour
Flag of PAKISTAN
rawalpindi, pakistan
$5 USD / hour
It's currently 4:31 AM here
Joined May 5, 2019
1 Recommendation

Junaid A.

@Ahmedjunaid339

3.4 (1 review)
2.2
2.2
0%
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$5 USD / hour
Flag of PAKISTAN
rawalpindi, pakistan
$5 USD / hour
100%
Jobs Completed
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On Budget
100%
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Embedded System Design (FPGA, RISCV, ARM)

Strong embedded development experience in heterogeneous architectures. Multifaceted experience in RTL design of RISCV cores, UVM verification methodology, proven knowledge of developing embedded devices and FPGA design, synthesis, implementation, placement, routing, timing analysis, etc. Core competencies: • Digital System Design (FPGA, CPLD) • IP Development and IP Onboarding • RISCV Cores • Computer Architecture • UVM • Artificial Intelligence Hands on experience on following hardware platforms: 1) ZYNQ Ultra Scale ME-XU1-6EG-1i-D11E Enclustra Mercury board. 2) Xilinx heterogeneous architectures: ZYNQ 7020, 7035 and 7045 FPGAs. 3) ZYNQ 702 and 706 FPGA boards. 4) Xilinx low power FPGAs Artix 7, Nexys 2,3 and 4 boards. 5) Xilinx low density Spartan FPGAs. Spartan 3E FPGA development kit. 6) Trenz TE0782 & TE0783 SOM FPGA boards. 7) Intel: Cyclone 10 FPGA development kit. 8) Intel: Cyclone 5 DE-10 nano and lite 9) Altera: DE2-115 FPGA development kit 10) Raspberry Pi 3B. 11) ARM Cortex STM32F407 Discovery board. 12) Analog devices: Realtime 3G/4G SDR based ADI RF integrated devices. 13) Atmel AVR microcontroller ATmega16/32/328, Arduino (Uno, Mega & Nano), (PIC based) chip kit. Practical working experience of the following software’s: Synopsys inc: Verdi, VCS, Spyglass, Design Compiler Intel: Intel EDS, Intel Quartus, DS-5 (ARM Processors), NIOS 2, Modelsim- Altera Xilinx: VIVADO, Xilinx SDK, Xilinx ISE Others: Verilator, Proteus, ORCAD, MATLAB, Simulink, LabVIEW,Atmel AVR Studio, Altium, Dsch, Microwind, AutoCAD, Android studio, NI Multisim, etc

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3.4
€125.00 EUR
Good work understands VHDL
Verilog / VHDL
Machine Learning (ML)
Arduino
Signal Processing
+1 more
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Flag of Witali S.
@witalischweizer
3 years ago

Experience

Associate Design Engineer

Lampro Mellon
Jul 2020 - Present
I have been working on different domains from time to time. First I worked in the Chisel team and published the first Chisel manual on Github as co-author. In the RTL design team I lead the project of SweRV EL2 RISCV core implementation in Chisel. In the verification team, I am working as a team member, currently working on the UVM.

SOC Trainee Engineer

Lampro Mellon
Jan 2020 - Jun 2020 (5 months, 1 day)
I have been taught the following courses: Verilog, System Verilog, Scala, Chisel, Computer architecture, RISCV processors, C/C++, Chinese and English languages. The key responsibilities are to attend lectures, submit: labs, projects, online quizzes, presentations, and to pass the final test.

Design Engineer Embedded

AKSA-SDS
Sep 2018 - Jan 2020 (1 year, 4 months)
I worked on avionics and military projects. Following are the projects on which I have worked: Radar, Transponder, Interrogator and SDR based real-time transponder. Main target is to propose solutions and implement them on some suitable hardware then testing with quality assurance. Tasks: 1) Algorithm Design 2) Schematic design 3) Implementation 4) Trouble shooting 5) Testing.

Education

B.Sc Electronics Engineering

University of Engineering and Technology, Taxila, Pakistan 2014 - 2018
(4 years)

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