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$15 USD / hour
Flag of EGYPT
beni suef, egypt
$15 USD / hour
It's currently 4:48 PM here
Joined July 26, 2017
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Mohamed A.

@Mhmdgaber

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$15 USD / hour
Flag of EGYPT
beni suef, egypt
$15 USD / hour
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FPGA design and VLSI Engineer

3+ years of experience in Xilinx ( Spartan/Artix/ Vertix /Zynq ) FPGAs prototyping using HDL (Verilog) across multiple design tools, (Xilinx ISE , Altera Quartus and Vivado ) Expertise: RTL, FSM, synthesis, simulation using Isim and Modelsim, bitstream generation, timing/power/thermal analysis using Xilinx Power Estimator (XPE). --------------------------- 2 years of experience in image processing hardware: Expertise: Convolutional neural networks , image encryption/decryption, recognition and a published paper. ------------------------- 1 year of experience in digital VLSI design in cadence: Expertise: Schematic design, SpectreS simulation, CMOS layout, Design Rule Checking (DRC), Layout versus Schematic (LVS), Parasitic extraction and Post layout simulation. -------------------------- 6 months of experience in MIPS/ ARM assembly: Expertise: interrupt handlers, recursion, nested functions, stack management, link register, program counter and frame pointer.
Freelancer Verilog / VHDL Designers Egypt
See all Verilog / VHDL Designers in Egypt

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Portfolio

4212354
16-bit single cycle processor implementation in Altera Quartus using Verilog HDL. Schematic design and instruction set are both attached.
Altera Cyclone Iv FPGA; 16-bit single cycle processor
16-bit single cycle processor implementation in Altera Quartus using Verilog HDL. Schematic design and instruction set are both attached.
Altera Cyclone Iv FPGA; 16-bit single cycle processor
16-bit single cycle processor implementation in Altera Quartus using Verilog HDL. Schematic design and instruction set are both attached.
Altera Cyclone Iv FPGA; 16-bit single cycle processor
4212360
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
4212332
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
4212297
Implementation of FIR filter in ARM7 assembly
ARM assembly
4212284
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4212267
MIPS assembly
4212354
16-bit single cycle processor implementation in Altera Quartus using Verilog HDL. Schematic design and instruction set are both attached.
Altera Cyclone Iv FPGA; 16-bit single cycle processor
16-bit single cycle processor implementation in Altera Quartus using Verilog HDL. Schematic design and instruction set are both attached.
Altera Cyclone Iv FPGA; 16-bit single cycle processor
16-bit single cycle processor implementation in Altera Quartus using Verilog HDL. Schematic design and instruction set are both attached.
Altera Cyclone Iv FPGA; 16-bit single cycle processor
4212360
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
Dice game implementation using Verilog in Alter Quartus. The simulation was done in Modelsim and the design was tested on Zynq700 Xilinx Soc.
Xilinx Zynq SOC, Digital design; FSM-based Dice game
4212332
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
Energy efficient Hardware accelerator for convolution neural networks, implemented using Verilog in Spartan6 FPGA. The schematic design of the accelerator and power analysis using XPE ans snippet of Verilog code are attached.
Xilinx Spartan 6 FPGA-based CNN accelerator
4212297
Implementation of FIR filter in ARM7 assembly
ARM assembly
4212284
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4-bit Linear Feedback Shift Register implementation in Cadence platform using AMI 0.6 Micrometer technology.
VLSI- Cadence
4212267
MIPS assembly

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Experience

MIPS/ARM assembly--MARS and QTSPIM Simulators

Fiver
Aug 2017 - Present
Featured projects: -> Booth Multiplication algorithm. -> LCD, stepper motor and keypad interface with Intel 8825 chip. -> Huffman Image compression

Xilinx FPGA (Spartan/Artix/ Vertix /Zynq) Verilog Design

Mentor Graphics, Centre of Nano-Electronics Devices (CND) and Opto-Nano-Electronics (ONE) Lab.
May 2015 - Present
Featured projects: -> 4-state FSM controller for 19200 buad-rate UART using Verilog & Xilinx Zynq7000 -> O(n) 9-pipeline-stages accelerator to solve linear equations 3x faster than the previous state-of-the-art, using Verilog & Spartan 6 FPGA -> Energy-efficinet Convolutioanl nerual networks learning accelerator for image classification using verilog & Vertix 7 FPGA -> 32-bit piplened MIPS Processor using Verilog & Artix 6 FPGA

VLSI - Cadence

Centre of Nano-Electronics Devices
Feb 2017 - Apr 2018 (1 year, 2 months)
Featured project: -> Full custom design of 4-bit Linear feedback shift Register, LFSR on Cadence where -AMI 0.6µm was the adopted technology for the layout. -Diva was used for DRC and LVS. -SpectreS for post layout simulation.

Publications

A robust fuzzy logic-based real-time automatic camber detection and measurement in hot rolling mill.

Institute of Electronics and Electrical Engineers, IEEE
I was the first author of a computer-vision/Image processing research paper published in the Global Conference on Consumer Electronics GCCE, held in Kyoto, Japan in 2016.

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Top Skills

Verilog / VHDL
Embedded Software
Cryptography
Assembly
Digital Design

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