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$15 USD / hour
Flag of INDIA
roorkee, india
$15 USD / hour
It's currently 7:48 AM here
Joined May 25, 2020
1 Recommendation

Vokkapatla Vinendra S.

@vinendra77

 5.0 (34 reviews)
4.1
4.1
96%
96%
$15 USD / hour
Flag of INDIA
roorkee, india
$15 USD / hour
100%
Jobs Completed
91%
On Budget
100%
On Time
33%
Repeat Hire Rate

Digital design Engineer

Hi, i am [login to view URL] graduate from IIT Roorkee and working on Digital System design, RTL design , FPGA prototyping using Verilog and VHDL from last 3 years. As a Electrical and Electronics engineer, i have a good knowledge on Electrical Circuits, Digital Electronics, Analog Electronics and Finite State Machine with Data path (FSMD). And i have good programming knowledge in C, Python, Matlab. And also i have very good knowledge in Mathematics.
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Portfolio

6616254
Verilog code for performing Division of two numbers
6600411
PYTHON Code for handling EXCEL data
6600108
VHDL_code for finite state machine (fsm)
6600007
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
6616254
Verilog code for performing Division of two numbers
6600411
PYTHON Code for handling EXCEL data
6600108
VHDL_code for finite state machine (fsm)
6600007
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101
The following problem explains how a sequence 101 is detected using finite state machines (fsm). Once fsm is defined it can be easily converted to digital design by using D fliflops or JK flipflops. Here sequence detector for 101 is implemented by both D flipflops and JK fliflops.
Sequence detection 101

Reviews

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Showing 1 - 5 out of 34 reviews
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5.0
$45.00 CAD
Project for Vokkapatla Vinendra S. -- 5
Very knowledgeable, assisted me in all my projects and delivered on time!
C Programming
Python
Electrical Engineering
Mathematics
+1 more
A
Flag of Al-Amin L.
@alaminfadeyi
•
3 years ago
5.0
$55.00 CAD
Project for Vokkapatla Vinendra S. -- 4
I have worked with him several times now and he has never failed me!
C Programming
Python
Electrical Engineering
Mathematics
+1 more
A
Flag of Al-Amin L.
@alaminfadeyi
•
3 years ago
5.0
₹6,790.00 INR
RTL Designer (verilog) needed.
Delivered my work before time. Also, helped me to understand everything at time of delivery. Keynotes: Great personality, efficient, expert, patience.
Electronics
Verilog / VHDL
Electrical Engineering
FPGA
Electronic Design
User Avatar
Flag of Md Rasid A.
@mdrasid
•
3 years ago
5.0
$50.00 CAD
Project for Vokkapatla Vinendra S. -- 3
Delivered on time again. Amazing!!!
C Programming
Python
Electrical Engineering
Mathematics
+1 more
A
Flag of Al-Amin L.
@alaminfadeyi
•
3 years ago
5.0
$50.00 CAD
Project for Vokkapatla Vinendra S. -- 2
Will work with him again. Was amazing and patient through out.
C Programming
Python
Electrical Engineering
Mathematics
+1 more
A
Flag of Al-Amin L.
@alaminfadeyi
•
3 years ago

Education

MTech

Indian Institute of Technology, Roorkee, India 2017 - 2019
(2 years)

BTech

Acharya Nagarjuna Vishwavidhyalayamu, India 2011 - 2015
(4 years)

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Top Skills

Electrical Engineering 26
Python 19
C Programming 18
Mathematics 17
Analog Electronics 17

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