verilog and designing small task
$30-40 USD
Paid on delivery
Design a 3D-IC
I need help to design a 3D-IC consisting of 10 gates that have at least 3 TSVs by using Cadence tool.
Requirements:
1. Commented Verilog code for your design (code listing)
2. Verilog testbench for your code and results (code listing and output log file and screenshot )
3. Synthesized Verilog of your design from Synopsys Design Compiler (code listing and screenshot)
4. Chip layout of your design from Cadence Encounter Place & Route (screenshot)
Description:
- Verilog is a hardware description language (HDL) for developing and modeling circuits.
- The Cadence SimVision tool will help you simulate circuits that have been developed in Verilog.
- An RTL compiler takes an RTL version of a design (such as Verilog) and transforms (compiles) the RTL by mapping the design to components in a standard cell library (such as logic gates).
- Place and Route – Cadence Encounter
Thank you,
Project ID: #4476608
About the project
4 freelancers are bidding on average $189 for this job
I am a digital design engineer, I use these tools normally with legal license , but I havent yet designed any 3D IC, I can try to do that without obligation if you want.
