Bus Function Model (verilog coding)

Dear sir I have more than 9 years experience in digital design using verilog, please check my profile also please message me so that we can discuss

Dear Sir/Madam, I’m write this letter to apply for the vacant at your project I have learned in HCM university of technology, I am an logic design engineer. I am working in Arrive Technologies Viet Nam two years. Through my courses at university and my company, I able to work on digital ASIC, FPGA design, knowledge of network and data communication (Carrier ethernet)....Therefore, I think I can fit in that project

Hi, I am an ASIC engineer with M.S. degree in electrical engineering. I have extensive experience in digital logic design as well as Verilog coding. Also, I have the experience of implementing I2C BFM, and have the I2C Slave Controller Verilog codes at hands, which may meet your requirement. I would like to talk to you about more details of this project, and I look forward to hearing from you. Thank you!

hello, currently i am working on verification of I2C protocol master model. So. i can give you bfm and test benches which i made fresh. I tested it in modelsim simulator and it is in working condition. All the require tasks is included in bfm.

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