Hello,
I can help you with your project, as I have experience in VHDL modeling and SoC programming.
Her a bit about me:
I'm Mohamed Maged, an experienced RTL engineer proficient in Verilog, SystemVerilog, and VHDL. I can efficiently handle your project and deliver high-quality results promptly. Your cooperation is key to creating an excellent work environment.
I have extensive experience with both FPGAs and ASICs, having worked with various FPGA boards, including MAX Family, DE-series, Cyclone V, ZYNQ, PYNQ, Basys3, Artix7, and Efinix T120, using tools like Vivado, Vitis HLS, Quartus, and Efinity. For ASIC design, I am well-versed in Synopsys tools, utilizing TCL scripts and GUI for tasks such as DesignCompiler, Formality, and DFT.
You can find examples of my previous work in my profile, where I've successfully completed complex designs in diverse fields, including image processing, cryptography, communication protocols, processors, and more.
I'm eager to collaborate with you and discuss the details of your project. Please feel free to reach out, and I'll be ready to assist you.
Have a great day,
M. Maged