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    601 project altera de1 jobs found, pricing in USD
    RISC-V microcontroller design in altera D2-115 FPGA t(looking for teacher) Ended

    1. You have to teach us about RISC-V microcontroller architecture top to bottom and instructions . 2. You have to teach us about VHDL / VERILOG. 3. You can deal it with logisim software. 4. You have to give support and help us to build RISC-V microcontroller in FPGA. 5. You can take class about these minimum 2 days in online. 6. You will get 4 month to complete this. You will get 150$ as payment as a teacher. Payment can't be increased cause we are student(cause it is our saving money :) )

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $197 (Avg Bid)
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    Development of Device Drivers for Linux Kernel on FPGA Altera Cyclone VSoC -- 2 Ended

    Tasks and scheduling Interruptions Race Direct access to peripherals

    Electronics FPGA Coding Linux Microcontroller Verilog / VHDL
    $197 (Avg Bid)
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    3 bids
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    CPLD converter, dual I2S codecs to TDM Ended

    The project's goal is to have two I2S codecs, both at the same samplerate, selectable 48/96/192KHz, connected to a CPLD and the CPLD to provide a TDM protocol for connection to a MCU. Codecs will have 48/96/192KHz, stereo, 32bits sample depth and will work at I2S prot...taken into consideration in order to better understand the requirements: 1. the freelancer must have good kowledge of audio TDM and I2S protocols. 2. The freelancer should decide what CPLD is most appropriate and cost beneficial to the task, CPLD has to be a member of Intel/Altera MAX V CPLD. 3. The freelancer will provide appropriate testbech to verify the proper behaviour of the design with written instructions on how to perform the tests. 4. The freelancer should provide all the sources and the complete Qua...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $172 (Avg Bid)
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    3 bids
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    Assembly using Altera Monitor Program Ended

    Assembly using Altera Monitor Program

    Assembly C Programming Microcontroller Verilog / VHDL x86/x64 Assembler
    $13 (Avg Bid)
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    2 bids
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    Signal aquisition using AD9226+FPGA+SDRAM Ended

    I need to get 4 miliseconds data from AD9226 12bit ADC using ALTERA EP4CE6E22C8 + HY57V561620FTP-H 256Mbit SDRAM when I push a button B1. When I push second time the button B1, to get another 4 ms of data. When I push another button B2, the data from SDRAM must be sent to a CP2102 TTL-USB adapter at 115200 baud rate, so I can donwload data to PC. The aquisition speed needs to be 65MHz.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $231 (Avg Bid)
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    12 bids
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    system verilog expert needed Ended

    I want long term employee. altera quartus II is needed. its simple project

    Electrical Engineering Engineering Matlab and Mathematica Physics
    $12 / hr (Avg Bid)
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    VHDL code in Quartus software and de-soc board Ended

    This Project is to code exercises on latches, flip-flops and registers along with switches, lights and multiplexers VHDL -- Quartus Prime Lite 18.1 Quartus. Altera De-Soc board hardware implementation

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $20 (Avg Bid)
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    5 bids
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    Board Application on DE1-socfpga Ended

    Basic device access subsystem I need help . Someone who can explain me and show me step by step how developpe a Control framework for access to LED, switch and 7-segment display devices for DE1-SoC(Microcontroller) , and then do Miscellaneous Device Drivers.

    Arduino C Programming Electrical Engineering Electronics Microcontroller
    $13 / hr (Avg Bid)
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    Build serial synchronous active data splitter using FPGA Ended

    It is a serial data splitter from 1 input source to 16 output sink using FPGA with specification as below: * synchronous data transfer * simplex data transfer (from source to sink), using TxD, RxD, TxClock , RxClock * there are 2 modes of clock operation which is selectable using gpio pin : external clock source or inte...splitter from 1 input source to 16 output sink using FPGA with specification as below: * synchronous data transfer * simplex data transfer (from source to sink), using TxD, RxD, TxClock , RxClock * there are 2 modes of clock operation which is selectable using gpio pin : external clock source or internal clock source * data buffer for input and all output channel * preferable to use low cost FPGA : Altera Cyclone II EP2C5T144 or you can recommend another low cost...

    FPGA Verilog / VHDL
    $529 (Avg Bid)
    $529 Avg Bid
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    Write somewhat complex VHDL code to be tested on Altera DE2 board Ended

    The project here is to write multiple conditions/actions using VHDL format, that can all be displayed in 1 single program. And tested on an Altera DE2 board Port mapping could be okay but using relatively basic principles is ideal. That is (all are not required): Case statements Else / ElseIf Signals Variables Shift register Flip Flops Multiplexer / De-multiplexer Multibit adder Along with the code, pin assignments should be completed.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $110 (Avg Bid)
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    FPGA Design | Analog Potentiometer to RGB LED Ended

    I need a design implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer (A/P) control RGB LEDs (document attached). Ideally the potentiometer would control the brightness of one of the colors and be able to switch between red, green, or blue. This does not need to actually be programmed onto the board. The schematic, code, and test benching just needs to be done. In addition, I need a brief description of what your inputs/outputs on your design are doing and how the decoder works. What you will provide (An example of your results is shown) - TOP Level Schematic for A/P to RGB LED - Decoder System Verilog Code - Test Bench (Model Sim) for A/P to LED RGB LED Data Link:

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $20 (Avg Bid)
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    FPGA Design | Analog Potentiometer to Control RGB LEDs Ended

    I need a design to be theoretically implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer control RGB LEDs (document attached). In addition, I need a rough description of what your inputs/outputs on your design are doing and how the decoder works. What you will provide (An example of your results is shown) - TOP Level Schematic for A/P to RGB LED - Decoder HDL - Simulatation for A/P to LED RGB LED Data Link:

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $100 (Avg Bid)
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    Need to build a Frogger game in Verilog using Altera board Ended

    I need help in making a Frogger game in Verilog and need to use 7-sig Altera board

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $225 (Avg Bid)
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    Need to build a Frogger game in Verilog Ended

    I need help in making a Frogger game in Verilog and need to use 7-sig Altera board

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $200 (Avg Bid)
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    Verilog code for a UART for ALtera FPGA Ended

    Design a UART transmitter to serially transmit data from the DE2 board via the serial link to a PC running a terminal program. The PC should then display the ASCII value of the data transmitted.

    FPGA Verilog / VHDL
    $42 (Avg Bid)
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    Need FPGA HCS08 Expert Ended

    Hi, I need FPGA HCS08 Expert we will be using HCS08 DE1 MicroController. more details i will share in chat box. please if you have experience relegated to this bid. thanks.

    Arduino Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $167 (Avg Bid)
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    Altera de1 board code changing in C language Ended

    Altera de1 board code changing in C language i already have the solution need a new code based on this one so simple change it for me

    C Programming Electrical Engineering FPGA Microcontroller Verilog / VHDL
    $116 (Avg Bid)
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    Embedded system -FPGA verilog code and do file using QUARTUS Prime lite,cyclone IV E Ended

    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write action. In this case, the 50 MHz clock signal available on the FPGA board is used as an input to increase the RAM address. The 3-bit data value written to a memory location at an address should represent the number of ones in the 7 address bits. For example, a value of 011 (=3) should be written to the location with an address of 1000011. •Once the first push-button...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $71 (Avg Bid)
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    Design an FPGA ready CPU Tutorial Ended

    I need a small CPU project prepared, to teach and demonstrate CPU construction. It should be able to fit on an Intel Altera. It should use RISC. The key components are the ability to explain why cache's were chosen, why addressing was chosen, and what options existed. 8-bits. It should be built using blocks, such that I can remove a block, and code in my own block, and assuming all is good, will result in no change of system. And of course, machine language codes. This will be used to teach an AP class. System Verilog. is a great example of what I am looking to teach with an FPGA

    Electrical Engineering Electronics FPGA
    $525 (Avg Bid)
    $525 Avg Bid
    3 bids
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    Embedded -Verilog Code for DE0-Nano board -- 2 Ended

    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory write action. In this case, the 50 MHz clock signal available on the FPGA board is used as an input to increase the RAM address. The 3-bit data value written to a memory location at an address should represent the number of ones in the 7 address bits. For example, a value of 011 (=3) should be written to the location with an address of 1000011. Once the first push-button ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $135 (Avg Bid)
    $135 Avg Bid
    3 bids
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    Verilog Code for DE0-Nano board Ended

    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory write action. In this case, the 50 MHz clock signal available on the FPGA board is used as an input to increase the RAM address. The 3-bit data value written to a memory location at an address should represent the number of ones in the 7 address bits. For example, a value of 011 (=3) should be written to the location with an address of 1000011. Once the first push-button ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $10 - $30
    $10 - $30
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    I/O VGA and Input Ended

    I am building a maze game from the ground up, the assembler, data path etc. I need some help with the VGA controller and input. This will be an on going project but for this part I need to get the input working. I am using Quartas to write it and Im using the DE1-SoC FPGA Im going to use the PS/2 port for the input using the arrow keys to move the character. For now I would just like to get the input working so I would like to push the arrow keys and have something appear on the screen. For example If I push the up arrow a red square is displayed while it is depressed. Attached is some code I have done so far.

    Electronics FPGA Microcontroller Verilog / VHDL
    $21 / hr (Avg Bid)
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    embedded systems (fpga) Ended

    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write action. In this case, the 50 MHz clock signal available on the FPGA board is used as an input to increase the RAM address. The 3-bit data value written to a memory location at an address should represent the number of ones in the 7 address bits. For example, a value of 011 (=3) should be written to the location with an address of 1000011. •Once the first push-button...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $54 (Avg Bid)
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    6 bids
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    Need help with Altera Cyclone IV E Ended

    Need an extra eyes to review my Altera design. You must has done a design with Altera Cyclone IV E. If you can show me that you have a design with Cyclone IV E, you are in. What I need from you is to review my Cyclone schematic, it should from 1 to 2 hours total. I had problem with configuration chip with my Cyclone IV E FPGA, need your help.

    Circuit Design Electrical Engineering Electronics Engineering
    $57 / hr (Avg Bid)
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    CAN to UART Converter on Altera Cyclone IV FPGA Ended

    There is a device that uses CAN with an 250k. baudrate It is necessary to read data by a specific ID and send to UART. Also receive data from UART and send by specific ID to CAN. The firmware must be added to the finished Cypress project, which also uses UART. UART 1M baudrate.

    Arduino Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $127 (Avg Bid)
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    Program NIOS II processor core (Cyclone IV E) using Eclipse in DE2-115 board Ended

    I am using Altera DE2-115 FPGA board to configure it using Quartus software 17 lite edition. We have to use QSYS to assign addresses and link the processor, then assign inputs and outputs in VHDL and pin planner in Quartus, and then use NIOS II processor for Eclipse to write a program in C and run the board. I am seeking some help in building this mini thing. I am attaching a pdf file for the task, Its two part (above and below). I have done the above part, and seeking help in the below one. In addition, I will send you a complete project file for the above part, and I need you to follow it and modify it according to the below part of the pdf file.

    C Programming FPGA Microcontroller Parallel Processing Verilog / VHDL
    $24 / hr (Avg Bid)
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    FIR filter Design using FPGA Ended

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

    C++ Programming FPGA Verilog / VHDL
    $94 (Avg Bid)
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    Build Project - Altera DE2-115 FPGA board Ended

    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $25 (Avg Bid)
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    Program a project Ended

    I am a worker for a software company. I am currently using Altera DE2-115 FPGA board to configure it using Quartus software. We have to use NIOS II processor, QSYS, and Eclipse to write a program and to run the board. I am seeking some help in building this mini thing.

    C Programming Electronics FPGA Microcontroller Verilog / VHDL
    $16 / hr (Avg Bid)
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    Project for Jin Q. Ended

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the value reaches more than 1$ green led comes on for one second to simulate a dispatched product..however, my code is glitchy...if you could help me fix it it'd be a life saver

    3D Design C++ Programming Electrical Engineering Embedded Software Verilog / VHDL
    $30 - $30
    $30 - $30
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    Project for Nick B. Ended

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the value reaches more than 1$ green led comes on for one second to simulate a dispatched product..however, my code is glitchy...if you could help me fix it it'd be a life saver

    Circuit Design Electrical Engineering Electronics PCB Design and Layout PCB Layout
    $30 - $30
    $30 - $30
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    Project for Jin C. Ended

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life saver

    Circuit Design Electrical Engineering Electronics Microcontroller PCB Layout
    $30 - $30
    $30 - $30
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    Processor design project using System Verilog and Quartus Ended

    Pipelined dual thread core processor design using system verilog, quartus software and altera development board. Please read pdf for detailed information.

    C Programming Electrical Engineering FPGA Software Architecture Verilog / VHDL
    $180 (Avg Bid)
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    FPGA verilog UART Ended

    I want the verilog UART code along with pin assignment, synthesis and waveform outputs using Quartus II tool on ALTERA DE2 Board.

    Electrical Engineering FPGA Verilog / VHDL
    $48 (Avg Bid)
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    verolig calculator Ended

    A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on the board (its due Saturday sharp)

    Electronics Engineering FPGA Microcontroller Verilog / VHDL
    $72 (Avg Bid)
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    Software development for Altera FPGA JAM programming from Embedded ARM Ended

    Project is to create C/C++ software to program Altera FPGA (MAX10) configuration memory from an embedded ARM processor using Altera JAM tools. The target device is MAX10 16M, and embedded CPU is Kinetis. The software must read a JAM file and program the FPGA configuration memory using the JTAG interface, which is bit-banged from the MCU pins. Deliverable is a C/C++ program for the JAM programming and a short description of the code. Developer will hand off to internal team for final integration. The dev hardware can be NXP Freedom K28F board (K28+16Mb DRAM) and any Intel (Altera) demo board for the MAX10 family. If you do not have this hardware, we can provide it for development. If we understand your experience, I will hire you immediately.

    C Programming C++ Programming Electrical Engineering Electronics Microcontroller
    $1500 (Avg Bid)
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    Dice game on Quartus II Ended

    I have a project coming up ‪in less than 12 hours‬. I would appreciate if you can help me individually in doing the project in anyway at a deal that shall satisfy your effort. please take a look at the instructions and let me know if you can help: You will use the Altera DE2-115 board (Side note: you only need to design the software and I will install it to the board myself), Quartus II software to design a dice game. In this game, two players take turns to roll simulated dice and whoever has a bigger number wins.  The requirements are as follows: * 7-segment displays Hex 7 and Hex 0 are used to display Player 1 and Player 2's numbers, respectively. In the initial state when the board rst boots up, number zero should be displayed on both 7-segment displays a...

    C Programming C++ Programming Electronics Microcontroller Verilog / VHDL
    $293 (Avg Bid)
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    Help on a simple Altera FPGA test case Ended

    Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip enable (active low) for the data bus to be enabled for read/write and a pin that indicates FIFO has reached its 3/4 capacity. Inside the FPGA will be a single FIFO with 1024 words that data will be written to it via the 16bit bus and read again via the 16bit bus. FIFO will have 48bits word length. What is required is the complete Quartus project with source rtl files and a testbech t...

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $175 (Avg Bid)
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    FFT implementation on Altera FPGA board Ended

    Please find attached file to read more about the project

    Electrical Engineering FPGA Matlab and Mathematica Microcontroller Verilog / VHDL
    $2229 (Avg Bid)
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    Skilled Altium Layout Designer Ended

    To Layout with Altium 8-10 layers board with Altera 484 BGA chip and DDR Memory on it. Will need English speaking guy in order to communicate with Schematic engineer for any pin swapping or other questions during the Layout. Estiamted lead time for the project - 2 weeks (8 hours per day). Attached snapshot on the board with component dumped around it.

    CAD/CAM Circuit Design Electrical Engineering Electronics PCB Layout
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    VHDL project: Press the right number game Ended

    Need to develop a very simple game using VHDL, to be run on an Altera DE1-SoC FPGA board. The game will use as external 4x4 keypad which will be connected to the board via one of the GPIO ports on the board. Also the game will use some 7-segment displays on the board to display some information regarding the game. The game itself is quite simple and straightforward. The rules of the game and other project information are given in the attached ZIP file.

    Electronics Engineering FPGA Programming Verilog / VHDL
    $390 (Avg Bid)
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    altera c5 soc fpga to hpc data transfer Ended

    I have 1.25 Mbps data on an avalon-ST interface to be transferred to the HPS then to the ethernet port on DE1-SOC board. The data are on 24 channels of 24bit samples. I need you to explain the work to me in case I need to modify it or change the platform. My project which collects the data is attached. The top-level file is i2s_dsp

    FPGA Verilog / VHDL
    $44 / hr (Avg Bid)
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    generate verilig code for quartus ii program Ended

    I have a de1-soc fpga board () for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    Electronics FPGA Matlab and Mathematica Verilog / VHDL
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    1024 point fft of the step signal on FPGA board Ended

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $368 (Avg Bid)
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    design with Altera FPGA Ended

    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

    Electronics FPGA Verilog / VHDL
    $275 (Avg Bid)
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    compile a list of audience -data research Ended

    I need around 500-1000 links gathered in batches (100 each) and will give you the criteria of how the search needs to be done with an example video sent to shortlisted applicants. hourly price is 2-3 USD, it is low but I always hire long term freelancers and give them regular work and will pay bonus if a good job is done. type DE1 on top of your bid so I know you have read my project. I also need to stress I take time in identifying who is best fit for my business and my customers, so have patience and answer questions asked. good luck

    Data Entry Data Processing Excel Research Web Search
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    Need Full time remote employee: FPGA Verilog Developer - Exciting opportunity to work on Blockchain Technology Ended

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting and growing Blockchain Technology + No contract. Job Requirement: - Most of job tasks are bound around Verilog programming and embedded systems. - Develop bitstream for different algorithms for variety of FPGA boards. - Code, simulate, synthesize and support to compile Verilog on FPGA. - Embedded Linux Development, VxWorks, RTEMS, or similar real-time operating systems. - C/C++, integrate software components, create and run unit te...

    C Programming Embedded Systems FPGA Linux Verilog / VHDL
    $13 / hr (Avg Bid)
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    FPGA with server Ended

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

    Arduino C Programming Electronics Microcontroller Verilog / VHDL
    $479 (Avg Bid)
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    FPGA Board Re-Evaluation Ended

    Hi Freelancers, I have a project I've been working on for the past 4 months- an Altera FPGA control system for a specific application. I’ve had the control system previously evaluated by an engineer, although there are aspects of the system I’d like to have double-checked prior to production. I’d like an Electrical Engineer to simply re-confirm my design, and advise on any mistakes I have made (e.g. resistance values, the need for bypass capacitors, etc...) The board is based on the Altera Cyclone 2 Platform (EP2C5T144), and involves Comparators, Optoisolators, SRAM, an ADC, an Op-Amp, an EPCS4 Device, and several Buck Converters & Regulators for Power Management. I believe the total re-evaluation time should be ~1 - 3 hours. My budget f...

    Circuit Design Electrical Engineering Electronics FPGA Microcontroller
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    Project for Nimrod M. Ended

    Hi Nimrod M., I noticed that you had previously bidded on my evaluation project for an Altera board approximately 3 weeks ago. Although the evaluation was completed, I’d like another engineer to re-evaluate the board and answer the remaining questions I have. As most problems have been solved, I believe the evaluation should take 2~3 Hours. My budget for re-evaluation is 100 AUD. Would you happen to be interested? Regards, Mihajlo

    Algorithm C Programming C++ Programming Circuit Design PCB Layout
    $66 (Avg Bid)
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